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24LC41
1K/4K 2.5V Dual Mode, Dual Port I2CTM Serial EEPROM
FEATURES
* Single supply with operation down to 2.5V * Completely implements DDC1TM/DDC2TM interface for monitor identification * Separate high speed 2-wire bus for microcontroller access to 4K-bit Serial EEPROM * Low power CMOS technology * 2 mA active current typical * 20 A standby current typical at 5.5V * Dual 2-wire serial interface bus * Hardware write-protect for both ports * Self-timed write cycle (including auto-erase) * Page-write buffer for up to 8 bytes (DDC port) or 16 bytes (4K Port) * 100 kHz (2.5V) and 400 kHz (5V) compatibility * 1,000,000 erase/write cycles guaranteed * Data retention > 40 years * 8-pin PDIP package * Available for extended temperature ranges +70C - Commercial (C): 0C to - Industrial (I): -40C to +85C
PACKAGE TYPE
PDIP DSCL VCLK/DWP VSS MSDA 1 2 3 4 24LC41 8 7 6 5 DSDA
VCC
MWP MSCL
BLOCK DIAGRAM
DDC Monitor Port DSDA EDID Table 1K Bit VCLK/DWP DSCL Microcontroller Access Port MSDA 4K Bit Serial EEPROM
DESCRIPTION
The Microchip Technology Inc. 24LC41 is a dual-port 128 x 8 and 512 x 8-bit Electrically Erasable PROM (EEPROM). This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Three modes of operation have been implemented: * Transmit-Only Mode for the DDC Monitor Port * Bi-directional Mode for the DDC Monitor Port * Bi-directional, industry-standard 2-wire bus for the 4K Microcontroller Access Port Upon power-up, the DDC Monitor Port will be in the Transmit-Only Mode, repeatedly sending a serial bit stream of the entire memory array contents, clocked by the VCLK/DWP pin. A valid high to low transition on the DSCL pin will cause the device to enter the bi-directional Mode, with byte-selectable read/write capability of the memory array. The 4K-bit microcontroller port is completely independent of the DDC port, therefore, it can be accessed continuously by a microcontroller without interrupting DDC transmission activity. The 24LC41 is available in a standard 8-pin PDIP package in both commercial and industrial temperature ranges.
MSCL
MWP
DDC is a trademark of the Video Electronics Standards Association. I2C is a trademark of Philips Corporation.
(c) 1996 Microchip Technology Inc.
DS21140B-page 1
This document was created with FrameMaker 4 0 4
24LC41
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name DSCL DSDA VCLK/DWP MSCL MSDA MWP VSS VCC
PIN FUNCTION TABLE
Function Serial Clock for DDC Bi-directional Mode (DDC2) Serial Address and Data I/O (DDC Bus) Serial Clock for DDC transmit-only mode (DDC1)/Write Protect Serial clock for 4K-bit MCU port Serial Address and Data I/O for 4K-bit MCU port Hardware write-protect for 4K-bit MCU port Ground +2.5V to +5.5V power supply
VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65C to +150C Ambient temp. with power applied ................ -65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins .................................................. 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +2.5V to 5.5V Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C Parameter Symbol VIH VIL VIH VIL VHYS VOL1 VOL2 ILI ILO CIN, COUT ICC Write ICC Read ICCS Min .7 VCC -- Max -- .3 VCC Units V V V V V V V A A pF mA mA A A VCC 2.7V (Note) VCC < 2.7V (Note) Note 1 IOL = 3 mA, VCC = 2.5V (Note) IOL = 6 mA, VCC = 2.5V VIN =.1V to VCC VOUT =.1V to VCC VCC = 5.0V (Note), Tamb = 25C, FCLK = 1 MHz VCC = 5.5V, DSCL or MSCL = 400 kHz VCC = 3.0V, DSDA or MSDA = DSCL or MSCL = VCC VCC = 5.5V, DSDA or MSDA = DSCL or MSCL = VCC Conditions
DSCL, DSDA, MSCL & MSDA pins: High level input voltage Low level input voltage Input levels on VCLK/DWP pin: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current
2.0 .8 -- .2 VCC .05 VCC -- -- .4 -- .6 -10 10 -10 10 -- 10 -- -- -- -- 3 1 60 200
Note:
This parameter is periodically sampled and not 100% tested.
DS21140B-page 2
(c) 1996 Microchip Technology Inc.
24LC41
TABLE 1-3: AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)
DDC Monitor Port (Bi-directional Mode) and Microcontroller Access Port Standard Mode Parameter Clock frequency (DSCL and MSCL) Clock high time (DSCL and MSCL) Clock low time (DSCL and MSCL) DSCL, DSDA, MSCL & MSDA rise time DSCL, DSDA, MSCL & MSDA fall time START condition hold time Symbol Min FCLK THIGH TLOW TR TF THD:STA -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Vcc = 4.5 - 5.5V Fast Mode Min -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2)
Units
Remarks
START condition setup time TSU:STA Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time THD:DAT TSU:DAT TSU:STO TAA TBUF
Output fall time from VIH min to VIL max Input filter spike suppression (DSCL, DSDA, MSCL & MSDA pins) Write cycle time
TOF TSP
-- --
250 50
20 + .1 CB --
250 50
ns ns
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3)
TWR
--
10
-- -- 600 1300 -- 0 10M
10 1000 -- -- 500 -- --
ms ns ns ns ns ns cycles
Byte or Page mode
DDC Monitor Port Transmit-Only Mode Parameters Output valid from VCLK/ -- 2000 TVAA DWP TVHIGH VCLK/DWP high time 4000 -- 4700 -- VCLK/DWP low time TVLOW Mode transition time TVHZ -- 500 Transmit-Only power up TVPU 0 -- time Endurance -- 10M --
25C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
(c) 1996 Microchip Technology Inc.
DS21140B-page 3
24LC41
2.0
2.1
FUNCTIONAL DESCRIPTION
DDC Monitor Port
The DDC Monitor Port operates in two modes, the Transmit-Only Mode and the bi-directional Mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input and sharing a common data line (DSDA). The device enters the TransmitOnly Mode upon power-up. In this mode, the device transmits data bits on the DSDA pin in response to a clock signal on the VCLK/DWP pin. The device will remain in this mode until a valid high to low transition is placed on the DSCL input. When a valid transition on DSCL is recognized, the device will switch into the bidirectional Mode. The only way to switch the device back to the Transmit-Only Mode is to remove power from the device. 2.1.1 TRANSMIT-ONLY MODE
In this mode, data is transmitted on the DSDA pin in 8bit bytes, each followed by a ninth, null bit (Figure 2-1). The clock source for the Transmit-Only Mode is provided on the VCLK/DWP pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted by most significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. The bi-directional Mode Clock (DSCL) pin must be held high for the device to remain in the TransmitOnly Mode. 2.1.2 INITIALIZATION PROCEDURE
The device will power up in the Transmit-Only Mode. This mode supports a unidirectional 2-wire protocol for transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Transmit-Only Mode (Section 2.1.2).
After VCC has stabilized, the device will be in the Transmit-Only Mode. Nine clock cycles on the VCLK/DWP pin must be given to the device for it to perform internal sychronization. During this period, the DSDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. The device will power up at an indeterminate byte address (Figure 2-2).
FIGURE 2-1:
DSCL
TRANSMIT-ONLY MODE
TVAA
TVAA
DSDA
Null Bit Bit 1 (LSB) Bit 1 (MSB) Bit 7
VCLK/DWP
TVHIGH FIGURE 2-2:
Vcc SCL
TVLOW
DEVICE INITIALIZATION
TVAA
TVAA
SDA
High Impedance for 9 clock cycles TVPU
Bit 8
Bit 7
VCLK/DWP
1
2
8
9
10
11
DS21140B-page 4
(c) 1996 Microchip Technology Inc.
24LC41
2.1.3 BI-DIRECTIONAL MODE
2.2
Microcontroller Access Port
The DDC Monitor Port can be switched into the bidirectional Mode (Figure 2-3) by applying a valid high to low transition on the bi-directional Mode Clock (DSCL). When the device has been switched into the bi-directional Mode, the VCLK/DWP input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a 2-wire bidirectional data transmission protocol. In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the bi-directional Mode Clock (DSCL), controls access to the bus and generates the START and STOP conditions, while the DDC Monitor Port acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
The Microcontroller Access Port supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (MSCL), controls the bus access, and generates the START and STOP conditions, while the Microcontroller Access Port works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
FIGURE 2-3:
MODE TRANSITION
Transmit Only Mode Bi-Directional Mode
DSCL
TVHZ
DSDA
VCLK/DWP
(c) 1996 Microchip Technology Inc.
DS21140B-page 5
24LC41
3.0 BI-DIRECTIONAL BUS CHARACTERISTICS
3.5 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit . Note: The microcontroller access port and the DDC Monitor Port (in bi-directional Mode) will not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the DSDA or MSDA line during the acknowledge clock pulse in such a way that the DSDA or MSDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
Characteristics for the bi-directional bus are identical for both the DDC Monitor Port (in bi-directional Mode) and the Microcontroller Access Port The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the DSDA or MSDA line while the clock (DSCL or MSCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
3.6
Device Addressing
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the DSDA or MSDA line while the clock (DSCL or MSCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion.
A control byte is the first byte received following the start condition from the master device. The first part of the control byte consists of a 4-bit control code. This control code is set as 1010 for both read and write operations and is the same for both the DDC Monitor Port and Microcontroller Access Port. The next three bits of the control byte are block select bits (B1, B2, and B0). All three of these bits are don't care bits for the DDC Monitor Port. The B2 and B1 bits are don't care bits for the Microcontroller Access Port, and the B0 bit is used by the Microcontroller Access Port to select which of the two 256 word blocks of memory are to be accessed (Figure 3-4). The B0 bit is effectively the most significant bit of the word address. The last bit of the control byte defines the operation to be performed. When set to one, a read operation is selected; when set to zero, a write operation is selected. Following the start condition, the device monitors the DSDA or MSDA bus checking the device type identifier being transmitted, upon a 1010 code the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the device will select a read or a write operation. The DDC Monitor Port and Microcontroller Access Port can be accessed simultaneously because they are completely independent of one another. Operation Read Write Control Code 1010 1010 Chip Select XXB0 XXB0 R/W 1 0
DS21140B-page 6
(c) 1996 Microchip Technology Inc.
24LC41
FIGURE 3-1:
DSCL or MSCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D) (D) (C) (A)
DSDA or MSDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
FIGURE 3-2:
BUS TIMING START/STOP
VHYS
MSCL or MSCL IN DSDA or MSDA IN
TSU:STA
THD:STA TSU:STO
START
STOP
FIGURE 3-3:
BUS TIMING DATA
TF THIGH TLOW TR
DSCL or MSCL TSU:STA IN
DSDA
OR
THD:DAT THD:STA TSP TAA THD:STA
TSU:DAT
TSU:STO
MSDA IN
TAA
TBUF
DSDA
OR
MSDA OUT
FIGURE 3-4:
START
CONTROL BYTE ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
X
X
X
X = Don't care. B0 is don't care for DDC Monitor Port, but is used by the Microcontroller Access Port to select which of the two 256 word blocks of memory are to be accessed.
(c) 1996 Microchip Technology Inc.
DS21140B-page 7
24LC41
4.0 WRITE OPERATION
Write operations are identical for the DDC Monitor Port (when in bi-directional Mode) and the Microcontroller Access Port, with the exception of the VCLK/DWP and MWP pins noted in the next sections. Data can be written using either a byte write or page write command. Write commands for the DDC Monitor Port and the Microcontroller Access Port are completely independent of one another. For the Microcontroller Access Port, the MWP pin must be held to VSS during the entire write operation.
4.2
Page Write
4.1
Byte Write
Following the start signal from the master, the slave address (4-bits), the chip select bits (3-bits) and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the port. After receiving another acknowledge signal from the port, the master device will transmit the data word to be written into the addressed memory location. The port acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time, the port will not generate acknowledge signals (Figure 4-1). For the DDC Monitor Port it is required that VCLK/DWP be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK/DWP can go low while the device is in its self-timed program operation and not affect programming.
The write control byte, word address, and the first data byte are transmitted to the port in the same way as in a byte write. But, instead of generating a stop condition, the master transmits up to eight data bytes to the DDC Monitor Port or 16 bytes to the Microcontroller Access Port, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order 5bits of the word address remains constant. If the master should transmit more than eight words to the DDC Monitor Port or 16 words to the Microcontroller Access Port prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2). For the DDC Monitor Port, it is required thatVCLK/DWP be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK/DWP can go low while the device is in its self-timed program operation and not affect programming. For the Microcontroller Access Port, the MWP pin must be held to VSS during the entire write operation.
FIGURE 4-1:
BUS ACTIVITY MASTER
BYTE WRITE
S T A R T CONTROL BYTE WORD ADDRESS DATA S T O P
SDA or MSDA LINE
S
A C K A C K A C K
P
BUS ACTIVITY VCLK
FIGURE 4-2:
BUS ACTIVITY MASTER
PAGE WRITE
S T A R T S T O P
CONTROL BYTE
WORD ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
SDA LINE BUS ACTIVITY
S
A C K A C K A C K A C K A C K
P
VCLK/DWP
DS21140B-page 8
(c) 1996 Microchip Technology Inc.
24LC41
5.0 ACKNOWLEDGE POLLING 6.0
6.1
WRITE PROTECTION
DDC Monitor Port
Acknowledge polling can be done for both the DDC Monitor Port (when in bi-directional Mode) and the Microcontroller Access Port. Since the port will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize but throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W=0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for the flow diagram.
When using the DDC Monitor Port in the bi-directional Mode, the VCLK/DWP pin operates as the write protect control pin. Setting VCLK/DWP high allows normal write operations, while setting VCLK/DWP low prevents writing to any location in the array. Connecting the VCLK/DWP pin to VSS would allow the DDC Monitor Port to operate as a serial ROM, although this configuration would prevent using the device in the TransmitOnly Mode.
6.2
Microcontroller Access Port
FIGURE 5-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The Microcontroller Access Port can be used as a serial ROM when the MWP pin is connected to VCC. Programming will be inhibited and the entire memory associated with the Microcontroller Access Port will be write-protected.
7.0
READ OPERATION
Send Stop Condition to Initiate Write Cycle
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. These operations are identical for both the DDC Monitor Port (in bi-directional Mode) and the Microcontroller Access Port and are completely independent of one another.
Send Start
7.1
Current Address Read
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
The port contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the port issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the port discontinues transmission (Figure 71).
7.2
Random Read
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the port as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. The master then issues the control byte again, but with the R/W bit set to a one. The port then issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition and the port discontinues transmission (Figure 7-2).
(c) 1996 Microchip Technology Inc.
DS21140B-page 9
24LC41
7.3 Sequential Read 7.4 Noise Protection
Sequential reads are initiated in the same way as a random read except that after the port transmits the first data byte, and the master issues an acknowledge as opposed to a stop condition in a random read. This directs the port to transmit the next sequentially addressed 8-bit word (Figure 7-3). To provide sequential reads, the port contains an internal address pointer, which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. Both the DDC Monitor Port and Microcontroller Access Port employ a VCC threshold detector circuit which disables the internal erase/write logic, if the VCC is below 1.5 volts at nominal conditions. The DSCL, MSCL, DSDA, and MSDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY MASTER
S T A R T CONTROL BYTE S T O P
DATA n
DSDA or MSDA LINE
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 7-2:
RANDOM READ
S T T S T A R T S T O P
BUS ACTIVITY A MASTER R
MSDA LINE
CONTROL BYTE
WORD ADDRESS (n)
CONTROL BYTE
DATA n
S
A C K A C K
S
A C K N O A C K
P
BUS ACTIVITY
FIGURE 7-3:
SEQUENTIAL READ
A C K A C K A C K S T O P
BUS ACTIVITY MASTER
DSDA or MSDA LINE
CONTROL BYTE
P
A C K DATA n DATA n + 1 DATA n + 2 DATA n + X N O A C K
BUS ACTIVITY
DS21140B-page 10
(c) 1996 Microchip Technology Inc.
24LC41
8.0
8.1
PIN DESCRIPTIONS
DSDA
8.4
MSCL
This pin is used to transfer addresses and data into and out of the DDC Monitor Port, when the device is in the bi-directional Mode. In the Transmit-Only Mode, which only allows data to be read from the device, data is also transferred on the DSDA pin. This pin is an open drain terminal, therefore the DSDA bus requires a pullup resistor to VCC (typical 10K for 100 kHz, 1K for 400 kHz). For normal data transfer in the bi-directional Mode, DSDA is allowed to change only during DSCL or MSDA low. Changes during DSCL high are reserved for indicating the START and STOP conditions.
This pin is the clock input for the Microcontroller Access Port, and is used to synchronize data transfer to and from the device.
8.5
MSDA
This pin is used to transfer addresses and data into and out of the Microcontroller Access Port. This pin is an open drain terminal, therefore the MSDA bus requires a pullup resistor to VCC (typical 10K for 100 kHz, 1K for 400 kHz). MSDA is allowed to change only during MSCL low. Changes during MSCL high are reserved for indicating the START and STOP conditions.
8.2
DSCL
8.6
MWP
This pin is the clock input for the DDC Monitor Port while in the bi-directional Mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-Only Mode to the bi-directional Mode. It must remain high for the chip to continue operation in the Transmit-Only Mode.
This pin is used to write protect the 4K memory array for the Microcontroller Access Port. This pin must be connected to either VSS or VCC. If tied to Vss, normal memory operation is enabled (read/write the entire memory). If tied to VCC, WRITE operations are inhibited. The entire memory will be write-protected. Read operations are not affected.
8.3
VCLK/DWP
This pin is the clock input for the DDC Monitor Port while in the Transmit-Only Mode. In the Transmit-Only Mode, each bit is clocked out on the rising edge of this signal. In the bi-directional Mode, a high logic level is required on this pin to enable write capability.
(c) 1996 Microchip Technology Inc.
DS21140B-page 11
24LC41
24LC41 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices.
24LC41
-
/P Package: Temperature Range: Device: P = Plastic DIP (300 mil), 8-lead Blank = 0C to +70C I = -40C to +85C 24LC41 Dual Mode, Dual Port I2C Serial EEPROM
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United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883
ASIA/PACIFIC
China Microchip Technology Unit 406 of Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hongiao District Shanghai, Peoples Republic of China Tel: 86 21 6275 5700 Fax: 011 86 21 6275 5060 Hong Kong Microchip Technology RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 India Microchip Technology No. 6, Legacy, Convent Road Bangalore 560 025 India Tel: 91 80 526 3148 Fax: 91 80 559 9840 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan, R.O.C Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139
JAPAN
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
Printed on recycled paper.
All rights reserved. (c) 1996 Microchip Technology Incorporated, USA. 9/96
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21140B-page 12
(c) 1996 Microchip Technology Inc.
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